Browsing by Subject VHDL
Showing results 1 to 12 of 12
| Issue Date | Title | Author(s) |
| 2011 | Arithmetic Logic Unit using VHDL | Singhal, Gourav; Singh, Anshuman; Singh, Shardul; Rai, Supriya; Balyan, Vipin [Guided by] |
| 2012 | Communication of Signals and Responses Leading To Cell Death Using Engineered Regulatory Networks | Jain, Shruti |
| 2012 | Communication of Signals and Responses Leading To Cell Death Using Engineered Regulatory Networks | Jain, Shruti; Naik, Pradeep K |
| 2009 | A Computaional Model For Cell Survival Death Using VHDL and MATLAB Simulator | - |
| 2009 | A Computational Model for Cell Survival Death Using VHDL and MATLAB Simulator | Jain, Shruti; Naik, Pradeep K.; Sharma, Rohit |
| 2008 | Design and Implementation of 64 Bit RISC Processor on VHDL | Sharma, Shashank; Animesh; Gupta, Sumit; Sharma, Rohit [Guided by] |
| 2025 | Digital System Design using Verilog HDL (21M11EC211) T-2 April, 2025 (Sem-2) ECE | - |
| 2024 | Digital System Design using Verilog HDL (21M11EC211) T-3 June, 2024 (Sem-2) CSE-IT,ECE,CE | - |
| 2025 | Digital System Design using Verilog HDL (21M11EC211) T-3 June, 2025 (Sem-2)M.Tech | - |
| 2024 | Digital System Design using VHDL (21M11EC211) T-1 February, 2024 (Sem-2) CSE, IT, ECE, CE | - |
| 2014 | To design 16-bit Microprocessor using VHDL | Bajpai, Ayush; Ranjan, Akhil [Guided by] |
| 2010 | Universal Asynchronous Receiver Transmitter (UART) | Dhiman, Ankur; Lakhanpal, Abhishek; Kumar, Rajat; Balyan, Vipin [Guided by] |
