Design of VLSI Interconnect Circuits for Energy Performance Optimization

Abstract

In deep submicron (DSM) technologies, such as those at 90 nm and lower, interconnects are crucial. In previous technologies, gate delay predominated over interconnect delay; however, this is no longer the case, and interconnect delays are becoming more and more significant. This is because, with DSM technologies, an interconnect cannot be viewed as a simple resistor; instead, accompanying parasitics like capacitance and inductance must also be taken into account. As a result, any signal that travels through one of these connections will always be delayed. One common method to cut down on (or eliminate) the delay is buffer insertion. This method involves inserting buffers at regular intervals along an interconnect to try and recover the signal each time the parasitics influence it. However, the switching times of buffers themselves vary. Therefore, a significant number of these buffers along an interconnect may add to the total latency in signal propagation. Buffer switching also adds to the loss of power. Furthermore, a significant issue with DSM technology is leakage power, and buffers have the potential to use power even when they are not switching. Therefore, it is imperative to develop methods that, in addition to decreasing total latency, also use less power—both dynamic and static. This thesis investigates a proposed interconnect structure (H-model) for both RC and RLC interconnect lines. The interconnect structures are proposed for two types of networks namely lumped and distributed network using L and π-models. An Elmore delay estimate is drawn for long wires and it is verified that for long wires delay increases with the square of interconnect length. To resolve this issue, Schmitt trigger and CMOS inverter using FinFET technology are used as a substitute for buffers to lower power and delay in interconnects. However, the focus is on the reduction of power consumption and dissipation to be able to be used for small portable devices. Hence, the buffers are implemented using Energy Recovery Techniques to reduce power consumption as well as power dissipation into the interconnect circuits. As a result, power is observed to be decreased yet, increasing the area of the chip. Further, to address the issue of area as well, current mode signalling is used to the interconnect circuits to reduce additional delay due to the large buffers added in between long wires. However, decrease in technology and wire geometry, long wires (say 10mm) show introduction of inductance as a parasitic component in the interconnect circuits. This not only forces to study RLC lines but also the issues which come along with it such as coupling noise and distortion. Also, it is shown that the proposed H-model can be used for IoT applications with best results.