Performance Assessment of Devices Beyond the Scaling Limits- Doublegate and Surrounding-gate Mosfet

Abstract

Complementary Metal Oxide Semiconductor (CMOS) technology advancement for improving the system reliability, current drive, computational capability and integration density at lower cost has reached to a limit where the significant undesirable effects appear, which further poses tremendous challenges beyond the 45 nm technology node. Therefore, for the further advancement of technology this would also be beneficial for the circuit designers as well as the communication market come with the more innovative device structures. Among which the double-gate MOSFET, due to increase in the mobility, ideal sub-threshold slope, high drain current, reduced power consumption and screening of source end of the channel by the drain electric field, and the surrounding-gate MOSFET, due to increase in gate control and, low-off state current, have emerged as better alternative device structures for the reduced short channel effects and achieving a compact device with a much reduced dimension. In this dissertation, an analytical modeling of both the devices is performed with the help of Poisson equation and gradual channel approximation. Moreover, the expressions are derived using the surface potential model based on drift-diffusion approximation, which is important for the future requirement of the technology. The modeling of terminal charges and trans-capacitances are also presented which are further used for the circuit simulation. Finally, for the small-signal analysis, the trans-capacitances are used to yield the Y-parameters and S-parameters of the device, which would characterize the device for the specified frequency regime of the spectrum for the application as an amplifier and as a switch in the wireless communication transceiver, based on the power gain analysis and on-state switch circuit analysis, respectively. In addition to this, the influence of the Gaussian doping in vertical direction (across the radius) of the surrounding-gate MOSFET on the device performance based on certain assumptions is also presented.