Please use this identifier to cite or link to this item:
http://ir.juit.ac.in:8080/jspui/jspui/handle/123456789/9294Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Srivastava, Viranjay M. | - |
| dc.contributor.author | Yadav, K.S | - |
| dc.contributor.author | Singh, G. | - |
| dc.date.accessioned | 2023-01-18T08:59:49Z | - |
| dc.date.available | 2023-01-18T08:59:49Z | - |
| dc.date.issued | 2012 | - |
| dc.identifier.uri | http://ir.juit.ac.in:8080/jspui/jspui/handle/123456789/9294 | - |
| dc.language.iso | en | en_US |
| dc.publisher | Jaypee University of Information Technology, Solan, H.P. | en_US |
| dc.subject | 45-nm Nanotechnology | en_US |
| dc.subject | Radio frequency | en_US |
| dc.subject | CMOS | en_US |
| dc.subject | VLSI | en_US |
| dc.title | Optimization of drain current and voltage characteristics for DP4T double-gate RF CMOS switch at 45-nm technology | en_US |
| dc.type | Article | en_US |
| Appears in Collections: | Journal Articles | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Optimization of drain current and voltage characteristics for DP4T double-gate RF CMOS switch at 45-nm technology.pdf | 4.31 MB | Adobe PDF | View/Open |
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