Mobile Networks-on-Chip Mapping Algorithms for Optimization of Latency and Energy Consumption

Abstract

With the advancement in technology, it is now possible to integrate hundreds of cores onto single silicon semiconductor chip or silicon die. In order to provide communication between these cores, large number of resources are required and it leads to the communication problem in System-on- Chip (SoC), which is solved by introduction of Networks-on-Chip (NoC). NoC proves to be most efficient in terms of flexibility, scalability and parallelism. In this paper, the proposed mapping algorithms, Horological Mapping (HorMAP), Rotational Mapping (RtMAP) and Divide and Conquer Mapping (DACMAP) for mapping of tasks onto cores, basically concentrate on the optimization of latency, queuing time, service time and energy consumption of topology at constant bandwidth required. The experimental results discussed in this paper shows the comparison of proposed algorithms with traditional random mapping algorithm. In this paper, 2D mesh topology with XY routing is considered for the simulation of proposed algorithms